The LibreRT project has been making steady progress toward its goal of building an advanced, open software stack for real-time and accelerated computing across the embedded systems continuum. As we reach an important intermediate milestone, we are excited to share a summary of the five peer-reviewed publications our team has produced during 2024 and 2025. These papers span the core pillars of the project \u2014 from heterogeneous programming models and approximate computing to operating system kernel design and compiler support for emerging architectures \u2014 and collectively demonstrate the breadth and depth of our research effort.<\/p>\n\n\n\n
<\/p>\n\n\n\n The LibreRT project is funded under the National Recovery and Resilience Plan (NRRP), call for tender No. 104 published on 02\/02\/2022 by the Italian Ministry of University and Research (MUR), funded by the European Union \u2013 Next Generation EU, Mission 4, Component 1, CUP D53D23008590001 and CUP D53D23008600006.<\/em><\/p>\n","protected":false},"excerpt":{"rendered":" The LibreRT project has been making steady progress toward its goal of building an advanced, open software stack for real-time and accelerated computing across the embedded systems continuum. As we reach an important intermediate milestone, we are excited to share a summary of the five peer-reviewed publications our team has produced during 2024 and 2025.… Read More »LibreRT Research Milestones: A Look at Our 2024\u20132025 Publications<\/span><\/a><\/p>\n","protected":false},"author":1,"featured_media":375,"comment_status":"closed","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"neve_meta_sidebar":"","neve_meta_container":"","neve_meta_enable_content_width":"","neve_meta_content_width":0,"neve_meta_title_alignment":"","neve_meta_author_avatar":"","neve_post_elements_order":"","neve_meta_disable_header":"","neve_meta_disable_footer":"","neve_meta_disable_title":"","footnotes":""},"categories":[8],"tags":[10,9],"class_list":["post-373","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-news","tag-news","tag-publications"],"_links":{"self":[{"href":"https:\/\/librert.di.unisa.it\/index.php?rest_route=\/wp\/v2\/posts\/373","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/librert.di.unisa.it\/index.php?rest_route=\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/librert.di.unisa.it\/index.php?rest_route=\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/librert.di.unisa.it\/index.php?rest_route=\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/librert.di.unisa.it\/index.php?rest_route=%2Fwp%2Fv2%2Fcomments&post=373"}],"version-history":[{"count":1,"href":"https:\/\/librert.di.unisa.it\/index.php?rest_route=\/wp\/v2\/posts\/373\/revisions"}],"predecessor-version":[{"id":374,"href":"https:\/\/librert.di.unisa.it\/index.php?rest_route=\/wp\/v2\/posts\/373\/revisions\/374"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/librert.di.unisa.it\/index.php?rest_route=\/wp\/v2\/media\/375"}],"wp:attachment":[{"href":"https:\/\/librert.di.unisa.it\/index.php?rest_route=%2Fwp%2Fv2%2Fmedia&parent=373"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/librert.di.unisa.it\/index.php?rest_route=%2Fwp%2Fv2%2Fcategories&post=373"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/librert.di.unisa.it\/index.php?rest_route=%2Fwp%2Fv2%2Ftags&post=373"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}
Benchmarking SYCL 2020 Across Major GPU Vendors<\/strong>
Our journey in 2024 began with a contribution to the 12th International Workshop on OpenCL and SYCL (IWOCL ’24) held in Chicago. In the paper SYCL-Bench 2020: Benchmarking SYCL 2020 on AMD, Intel, and NVIDIA GPUs<\/em>, Luigi Crisci, Lorenzo Carpentieri, Peter Thoman, Aksel Alpay, Vincent Heuveline, and Biagio Cosenza presented an extended benchmark suite specifically designed to evaluate key features introduced in the SYCL 2020 standard, including unified shared memory, reduction kernels, specialization constants, group algorithms, in-order queues, and atomics. The suite was tested on GPUs from the three major vendors using two different SYCL implementations \u2014 AdaptiveCPP and oneAPI DPC++ \u2014 providing a rigorous and vendor-neutral assessment of SYCL 2020 maturity. This work lays a critical foundation for LibreRT’s broader mission of portable heterogeneous programming, as it gives us a clear picture of the state of the ecosystem on which we build.<\/p>\n\n\n\n
Toward Heterogeneous, Distributed, and Energy-Efficient Computing with SYCL<\/strong>
Also in 2024, Biagio Cosenza, gave a presention Toward Heterogeneous, Distributed, and Energy-Efficient Computing with SYCL<\/em> at the Scientific HPC in the pre-Exascale era workshop (SHPC), part of ITADATA 2024. This work introduced our broader research vision for extending SYCL semantics beyond single-node heterogeneous programming. The key insight is that SYCL’s high-level C++ abstractions can be naturally extended to address workload distribution on accelerator clusters (via the Celerity framework) and energy-efficient computing (via SYnergy). This paper sets the stage for LibreRT’s approach of building advanced features as composable extensions on top of the SYCL standard, rather than reinventing the wheel.<\/p>\n\n\n\n
Fluid Kernels: A New OS Architecture for the Embedded Continuum<\/strong>
Moving into 2025, Federico Terraneo and Daniele Cattaneo published Fluid Kernels: Seamlessly Conquering the Embedded Computing Continuum in the prestigious IEEE Transactions on Computers. This paper introduces a novel kernel architecture \u2014 fluid kernels \u2014 that represents the intersection between embedded unikernels and general-purpose monolithic kernels. The key innovation is the ability to seamlessly develop applications both in kernel space and user space in a unified way, enabling a scalable trade-off between performance, code size, isolation, and security. The concrete implementation, Miosix, was compared against both Linux and FreeRTOS on the same hardware. The results are impressive: compared to Linux, Miosix achieves an average speedup of 3.5\u00d7 (up to 15.4\u00d7) and an average code size reduction of 84%; compared to FreeRTOS, Miosix provides significant performance advantages at only a moderate code size cost. This work is central to LibreRT’s operating system layer for micro-edge devices and demonstrates the viability of our approach to bridging the embedded software fragmentation gap.<\/p>\n\n\n\n
SYprox: Approximate Computing Meets Heterogeneous Architectures<\/strong>
At the 39th ACM International Conference on Supercomputing (ICS ’25) held in Salt Lake City, Lorenzo Carpentieri and Biagio Cosenza presented SYprox: Combining Host and Device Perforation with Mixed Precision Approximation on Heterogeneous Architectures. SYprox is a SYCL-based approximate computing framework that allows programmers to easily implement heterogeneous approximated applications. It supports multiple techniques \u2014 data perforation, signal reconstruction, and mixed precision \u2014 and, critically, allows them to be combined. A distinctive contribution is the extension of existing perforation approaches to support both host and device data perforation, exploiting the full host-device execution model. The experimental evaluation showed that SYprox’s approximations are Pareto-dominant with respect to state-of-the-art approaches and are portable to AMD, Intel, and NVIDIA GPUs. SYprox is a cornerstone of LibreRT’s approximate computing and autotuning layer, providing the programmable mechanisms needed to trade accuracy for performance and energy efficiency under real-time constraints.<\/p>\n\n\n\n
Autovectorization on RISC-V: Exploring the RVV Frontier<\/strong>
Rounding out our 2025 publications, Lorenzo Carpentieri, Mohammad VazirPanah, and Biagio Cosenza presented A Performance Analysis of Autovectorization on RVV RISC-V Boards at the Euromicro International Conference on Parallel, Distributed and Network-based Processing (PDP 2025). This paper provides a thorough examination of autovectorization capabilities in GCC and LLVM for the RISC-V Vector Extension (RVV), evaluated on real hardware \u2014 the AllWinner D1 and BananaPi-F3 boards. Across 151 loops from the Test Suite for Vectorizing Compilers and seven real-world applications, the study reveals that LLVM-19 outperforms GCC-14 in a majority of cases, and that tuning the vector Length Multiplier (LMUL) parameter can yield performance improvements of up to 3\u00d7. These findings are directly relevant to LibreRT’s compiler and code generation efforts, as RISC-V is an increasingly important target in the embedded computing continuum.
Looking Ahead<\/p>\n\n\n\n
These five publications represent a solid foundation, but the LibreRT project is far from complete. Our research is actively ongoing across all fronts: we are extending SYCL with real-time programming support, investigating new scheduling strategies for our real-time operating system, and developing the autotuning layer that will tie approximation accuracy to real-time constraints. Several new and exciting publications are already in the pipeline, and we look forward to sharing them with the community in the coming months. Stay tuned!<\/p>\n\n\n\n